On the implementation of an efficient performance driven generator for conditional-sum-adders
نویسندگان
چکیده
We present data structures and an eecient algorithm realizing eecient performance driven generation of integer adders. The generator is parameterized in n, the operands' bitlength, and tn, the delay of the addition. It outputs an area minimal n-bit adder of the conditional-sum type with delay tn, if such a circuit exists.
منابع مشابه
TO APPEAR IN : IEEE TRANSACTIONS ON CAD / ICAS 1 On the Generation of Area - Time OptimalTestable
| We present a performance driven generator for integer adders which has the following interesting feature: The generator is parametrized in the operands' bitlength n, the delay of the addition tn and the fault model FM. FM may in particular be chosen as the classical stuck-at fault model, the cellular fault model or the robust path delay fault model. The output of the generator is a performanc...
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